This invention relates, in general, to high speed digital communication, and more particularly, to non-return to zero (NRZ) serial data receiver clock synchronization.
High speed communication lines are capable of sending data at extremely fast rates. For example, NRZ data is sent as a stream of bit logic levels at speeds approaching 1.8 gigahertz. The high speed of data transfer imposes significant constraints on the tolerances of circuitry receiving data. One problem is the waveform of the data itself at high frequencies. The data does not appear as a pulse with well defined edge transitions, but looks more like a sine-wave at high frequencies. Error in detecting the logic state of such a data waveform is minimized by sampling the waveform in the middle of the data bit period as illustrated in FIG. 1.
NRZ data is sent at a predetermined frequency. The sender (or data transmitter) typically has an accurate oscillator operating at the predetermined frequency. The receiver has its own oscillator operating at the same predetermined frequency.. The receiver must know the data phase and frequency to detect the logic state in the middle of the data bit period. The data phase is only revealed by data transitions. The phase can be lost without data transitions because the receiver oscillator drifts with respect to the sender oscillator.
One approach to insure synchronization is to use dual gated slave oscillators that resynchronize the clock phase to incoming data transitions. A first example of such a system is described in "A 660 Mb/s CMOS Clock Recovery Circuit with instantaneous Locking for NRZ Data and Burst-Mode Transmission" by Mihai Banu and Alfred Dunlop, from the 1993 IEEE International Solid-State Circuits Conference which is hereby incorporated by reference. A second example is described in "Clock Recovery Circuits with Instantaneous Locking" by Mihai Banu and Alfred Dunlop, from Electronic Letters, Nov. 5th 1992, Vol. 28, No. 23, which is hereby incorporated by reference. The dual gated slave oscillators are started and stopped by a transitioning input signal. But it is important to note that only one oscillator operates at any time. The circuitry forces each oscillator to be in phase synchronization with the data once it is started.
A problem may occur when the data does not transition for an extended period of time. The NRZ data is asynchronous with respect to the clock of the receiver. If the clock drifts during the extended period of time a condition of metastability may occur. Metastability is a condition where clock and data are asynchronous with one another. A physical link protocol has been developed to eliminate this problem. A sync bit is inserted before each data byte to insure the receiver clock remains phase coherent with the NRZ data.
There will be times when the communication lines are idle. A free running receiver clock will drift during the idle time. The receiver clock becomes asynchronous with data that is input after the idle time. If this occurs there is a possibility of metastability. A sync bit cannot be used during the idle time because the receiver circuit would assume that data is being transmitted.
Hence, it would be of great benefit if a serial data receiver clock synchronization circuit could be developed which eliminates the possibility of metastability after an idle period in data transmission.